1. Field of the Invention
The present invention relates to the field of the functional testing of logic integrated circuits or integrated circuits including logic portions.
2. Discussion of the Related Art
The production of an integrated circuit generally includes steps of testing of the manufactured circuits. The manufacturing can itself be, possibly, aimed at a testing, when a new circuit has to be validated or the manufacturing of a circuit has to be transferred from a known technology to a new technology.
These tests are usually of two types: structural tests, on the one hand, and functional tests, on the other hand. Structural tests have the object of checking that the circuits have no physical defects which make them inoperative, these defects being independent from the applications of the circuits. Functional tests have the object of checking, for circuits exhibiting no physical defects, that these circuits operate properly for the applications for which they are meant.
These tests, generally driven by automated test machines, can be performed before encapsulation, by means of probes enabling to have access to the circuit access pads. They can also be performed after encapsulation, by having access to the circuit through its access leads.
A method to implement the functional tests is to send logic signals on the inputs (pads or leads) of the circuit to be tested, observing the states of the signals provided on its outputs (pads or leads) and comparing these states with the states theoretically expected. The states of the provided logic signals form what is usually called test patterns or vectors.
Since it is desired to continually decrease the surface of circuits while increasing the circuit integration and operating frequency, this method has several disadvantages.
First, in practice, the number of circuit inputs and outputs does not increase proportionally to the increasing complexity of the circuits. The decrease in the minimum manufacturing resolutions allows more and more complex circuits, for an equal surface, while the number of pads increases little. Indeed, this number of pads is a function of the type of package in which the circuit is to be inserted. Now, the size of the leads has to be large enough to enable a reliable welding of its leads and, proportionally, this size decreases slower than the minimum manufacturing resolutions. Since, moreover, it is generally desired to limit the surface area occupied by the circuits, this results in an increase in the number of internal circuits which are not directly accessible from the outside of the circuits. A problem of access to internal circuit elements thus arises during the tests. This is even more of a problem for circuits including, for example, internal processors using peripherals without any relation to the outside, such as program memories or dynamic memories. Internal compound testing devices made by means of shift registers disposed on the internal buses of the circuits and driven by external testing appliances may be implemented. Thereby, a better observability of the internal devices of the circuits is obtained. Indeed, a higher number of test signals can be provided, for an equal number of inputs and outputs, by using series inputs and outputs to provide the test vectors one by one and receive the states of the signals resulting from their taking into account by the circuit (these resulting states will be called resulting vectors hereafter). Conversely, this is done at the cost of the test duration since it is necessary, for each test step, to provide in series a test vector, and to receive the resulting vector. Further, a test can only be implemented step by step, which is little representative of the final operation of the tested circuit.
Another problem arises from the desire to have higher and higher performance circuits in terms of operating frequency. Indeed, for their results to be representative, the tests must be performed in normal operating conditions. This amounts, in practice, to using wide pass-band testing devices, able to provide and sample signals at the operating frequencies of these circuits, these frequencies being likely to reach several hundreds of megahertz. This sets problems of implementation of the testing devices, for example, as concerns the probes needed to access to the circuit pads or leads.
Another problem arises from the possible presence of internal circuits operating at a higher operating frequency than the internal interface circuits. Internal interface circuits are generally sized with respect to the loads that they have to withstand on the input and output pads or leads. There is a tendency to use buffer circuits, capable of providing high currents, but the performances of which are limited in terms of operating frequency, to avoid a very high power consumption. Conversely, to implement the internal logic circuits, higher frequencies may be used, the loads withstood by these circuits being generally low. If such is the case, these logic circuits will be difficult to test since, even if access can be had to these circuits via the pads or leads, the frequency will be limited by the interface circuits.
A solution to these problems is to use automated testing devices disposed in the circuits to perform functional tests, and controlled by programs disposed in the circuits.
A first problem caused by this type of solution is the surface area occupied by these internal testing resources. This surface area is occupied at the cost of the surface area occupied by the circuits actually used in the applications, which limits the useful functional surface of the circuits, and this, all the more as the tests are more complex.
The surface of these devices may be, possibly, limited by using, during tests, resources subsequently used in the applications. For example, for circuits including an internal processor, an additional memory including a test program implemented by this processor can simply be provided. A problem then is to ensure satisfactory test coverage, especially for the internal resources used to implement the test program. In the implementation of the tests, this can also cause problems in terms of control, such as the impossibility of being able to act on the tested circuit if a blocking occurs within the tested circuit.
On the other hand, such integrated devices do not offer a flexibility similar to that offered by external devices, in the implementation of the tests. For example, modifying a test program can force modification of the circuit, unless a memory accessible from the outside is available, which is not justified if this memory is used for the testing only.
An aim of the present invention is to provide an improved method of testing of integrated circuits, which overcomes the pass-band problem linked to testing devices and to internal interface circuits.
Another object of the present invention is to provide a testing method which provides a good observability of the internal operation of the tested circuits.
Another aim of the present invention is to provide a method which does not require any internal device using a significant surface area of the circuit to be tested.
Another aim of the present invention is to provide a method which offers extended possibilities in terms of testing.
Thus, the present invention provides a method of functional testing of an integrated circuit including at least one internal logic circuit to be tested, this internal logic circuit including at least one input and one output. The method includes:
providing at least one test pattern, formed of a set of logic states, on a first input of the integrated circuit, by series shifting, and storing this test pattern in a first test register, the providing step being synchronized by an external clock signal received on a second input of the integrated circuit,
serially providing this test pattern to the input of the internal logic circuit, this providing step being synchronized by a test clock signal generated from an internal clock signal generated in the integrated circuit, the first internal clock signal having a frequency higher than the frequency of the external clock signal,
storing, in a second test register connected to the output of the internal logic circuit, of at least one resulting pattern generated by the internal logic circuit when the test pattern is provided thereto, this storage being synchronized by the test clock signal, and
providing, by series shifting, on a first output of the integrated circuit, of the resulting pattern, this providing step being synchronized by the external clock signal.
According to an embodiment of the present invention, the internal clock signal is generated by a programmable ring oscillator.
According to an embodiment of the present invention, providing the test pattern to the internal logic circuit is performed by means of a parallel-to-series conversion circuit, so that this test pattern can be provided several times to the internal logic circuit, once this pattern has been stored in the first test register.
According to an embodiment of the present invention, the test clock signal is generated by time filtering of the internal clock signal, so that the operation of the internal logic circuit is limited in time to the duration necessary for this circuit to receive the test pattern and to generate the resulting pattern.
According to an embodiment of the present invention, the parallel-to-series conversion signal is driven by control signals, the generation of which is synchronized with the generation of the test clock signal, these control and test clock signals being provided to the parallel-to-series conversion circuit and to the internal logic circuit by means of programmable skew circuits, so that a time skew can be introduced between the control signals and the test clock signal.
The present invention also relates to an integrated circuit including an internal logic circuit and testing means for testing the operation of the internal logic circuit, this internal logic circuit including one input and one output.
The testing means include:
a first test register having an input connected to a first input of the integrated circuit and at least one output connected to the input of the internal logic circuit,
a second test register having an input connected to the output of the internal logic circuit and an output connected to a first output of the integrated circuit,
a second output for receiving an external clock signal to drive, on the one hand, the provision to the first test register of at least one test pattern received on the first input, this test pattern being formed of a set of logic states, and, on the other hand, the provision to the first output of at least one resulting pattern stored in the second test register, this resulting pattern being generated on the output of the internal logic circuit when the test pattern is provided to the input of the internal logic circuit,
a clock signal generation circuit for generating an internal clock signal, and
a control circuit for providing, based on the internal clock signal, a test clock signal that drives the provision of the test pattern to the input of the internal logic circuit and the provision of the resulting pattern to the input of the second test register.
According to an embodiment of the present invention, the circuit includes a second output and the testing means include a frequency dividing circuit receiving the internal clock signal and generating a derived internal clock signal, of lower frequency than the internal clock signal, this lower frequency being representative of the frequency of the internal clock signal, and the derived internal clock signal being provided to the second output of the integrated circuit.
According to an embodiment of the present invention, the clock signal generating circuit includes a first programmable delay circuit for generating a programmable delay and logic circuits that implement a ring oscillator programmable by looping back of an input and of an output of the first delay circuit.
According to an embodiment of the present invention, the first delay circuit of the clock signal generating circuit generates a square signal of programmable frequency and the clock signal generating circuit includes a second programmable delay circuit receiving the square signal and providing a delayed square signal, a logic gate generating an intermediary clock signal from a combination of the square signal and of the delayed square signal, so that the intermediary signal has a programmable duty ratio, and means for generating the internal clock signal from the intermediary clock signal.
According to an embodiment of the present invention, the circuit includes a parallel-to-series conversion circuit placed between the first test register and the input of the internal logic circuit and the control circuit generates one or several selection signals to drive the parallel-to-series conversion circuit, the selection signals being generated based on the internal clock signal.
According to an embodiment of the present invention, the control circuit includes, on the one hand, a circuit of generation of drive signals for generating a filtered clock signal and primary selection signals and, on the other hand, skew circuits receiving the filtered clock signal and the primary selection signals, these skew circuits including programmable delay circuits for generating, based on the received signals, the selection signals driving the parallel-to-series conversion circuit and the test clock signal, the selection signals driving the parallel-to-series conversion circuit being skewed with respect to the test clock signal.
According to an embodiment of the present invention, the control circuit includes filtering means for generating, based on the internal clock signal, in a so-called burst test mode, the test clock signal driving the operation of the internal logic circuit, this test clock signal including at least one pulse train including a determined number of pulses.
According to an embodiment of the present invention, the control circuit provides a logic signal representative of the duration of pulse trains in the burst test mode.
In the present invention, an external testing device is used to implement the test, which overcomes the problems linked to the use of tests by internal testing devices. To overcome the problem of the testing devices and interface circuit pass-band, the data exchanges between the testing device and the circuit to be tested are performed at a frequency compatible with normal operating frequencies of the testing device and of the interface circuits of the circuit to be tested. The test itself is performed in conditions compatible, in terms of frequency and of progress, with the normal operating conditions of the tested circuit, which obtains test results representative of this normal operation.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of an example embodiment in connection with the accompanying drawings.